1. Technical Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a method of manufacturing the non-volatile memory device. More particularly, exemplary embodiments of the present invention relate to a non-volatile memory device including a split floating gate and a method of manufacturing the non-volatile memory device.
2. Discussion of Related Art
Generally, a semiconductor memory device is classified into a volatile memory device that loses data over time, and a non-volatile memory device for example, a flash memory that continuously maintains stored data, regardless of the passage of time.
The non-volatile memory device may include a memory cell having a stacked gate structure or a memory cell having a split gate structure.
A flash memory device widely used for the non-volatile memory device includes a plurality of memory cells arranged in a matrix pattern of rows and columns. The flash memory device electrically programs or reads data in a single memory array or at least two memory arrays in memory cells. On the other hand, the flash memory device simultaneously erases all of the memory arrays in the memory cells.
The flash memory device is a progressive type of an electrically erasable programmable read only memory (EEPROM) capable of rapidly erasing data. The flash memory device electrically controls input/output of data using Fowler-Nordheim (F-N) tunneling or hot electrons.
While programming data of the non-volatile memory device, a positive voltage applied to a word line, that is, a control gate, is coupled to a floating gate. Electrons are captured in the floating gate from a semiconductor substrate through a tunnel oxide layer by the F-N tunneling effect, or a hot earner injection, to program the data in the non-volatile memory device. On the other hand, while erasing data from the non-volatile memory device, the electrons in the floating gate escape to the semiconductor substrate by a negative voltage applied to the word line, or to the word line by a positive voltage applied to the word line.
As a design rule of the non-volatile memory device has been reduced, however, a size of the memory cell layout has been shrunk. This worsens the program efficiency of the non-volatile memory device operated in accordance with the above-mentioned conditions. Further, the program efficiency may be mainly dependent on the mobility of the hot electrons. Therefore, as a width of the word line making contact with the semiconductor substrate has been narrowed, the worsened program efficiency brings about reduction of a cell current.
Furthermore, in a non-volatile memory device having a split floating gate, an overlapped region between the split floating gate and a common source region has a very small area, so that a coupling ratio may be very low.